`include "ysyx_23060189_cpu.svh"

module ysyx_23060189_MEU #(parameter xlen = 32) (
  input  wire            clk,
  input  wire            rst,
  // data: EXU <=> MEU
  input  wire [xlen-1:0] ex_inst,
  input  wire [xlen-1:0] ex_pc,
  input  wire [1:0]      ex_PC_sel,
  input  wire [1:0]      ex_st_type,
  input  wire [2:0]      ex_ld_type,
  input  wire [1:0]      ex_wb_sel,
  input  wire [2:0]      ex_csr_cmd,
  input  wire            ex_wb_en,
  input  wire            ex_br_taken,
  input  wire [xlen-1:0] ex_Alu_out,
  input  wire [4:0]      ex_wb_addr,
  input  wire [xlen-1:0] ex_rs2_data,

  input  wire            ex_valid,
  output wire            me_ready,

  // data: MEU <=> WBU
  output wire [xlen-1:0] me_inst,
  output wire [xlen-1:0] me_pc,
  output wire [1:0]      me_PC_sel,
  output wire [1:0]      me_wb_sel,
  output wire [2:0]      me_csr_cmd,
  output wire            me_wb_en,
  output wire            me_br_taken,
  output wire [xlen-1:0] me_Alu_out,
  output wire [4:0]      me_wb_addr,
  output wire [xlen-1:0] me_rd_data,

  output wire            me_valid,
  input  wire            wb_ready,

  // data:MEU <=> MEM
  output wire            meu_valid,
  output wire [xlen-1:0] addr,
  output wire [1:0]      st_type,
  output wire [2:0]      ld_type,
  output wire [xlen-1:0] wr_data,
  input  wire [xlen-1:0] rd_data,
  input  wire            mem_valid
);

  // data: MEU <=> WBU
  assign me_inst     = ex_inst;
  assign me_pc       = ex_pc;
  assign me_PC_sel   = ex_PC_sel;
  assign me_wb_sel   = ex_wb_sel;
  assign me_csr_cmd  = ex_csr_cmd;
  assign me_wb_en    = ex_wb_en;
  assign me_br_taken = ex_br_taken;
  assign me_Alu_out  = ex_Alu_out;
  assign me_wb_addr  = ex_wb_addr;
  assign me_rd_data  = rd_data;

  assign me_valid    = ex_valid & mem_valid;
  assign me_ready    = 1;

  // data:MEU <=> MEM
  assign meu_valid = ex_valid;
  assign addr     = ex_Alu_out;
  assign st_type  = ex_valid == 1 ? ex_st_type : `ysyx_23060189_ST_XXX;
  assign ld_type  = ex_valid == 1 ? ex_ld_type : `ysyx_23060189_LD_XXX;
  assign wr_data  = ex_rs2_data;

endmodule
